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  3. Using interface signals as coverpoint bins

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Using interface signals as coverpoint bins

RajeshCM
RajeshCM over 13 years ago

Hi,

 I have my functional coverage like this:

class mem_cov_grp;

virtual SysRegIntf;

covergroup walks();

level:      coverpoint SysRegIntf.Addr {

                 bins MAX = {31- SysRegIntf.Tag};

                 bins MAX_PLUS_ONE = {31 - SysRegIntf.Tag + 1}; 

              }  

endgroup 

function new (Virtual SysRegIntf);

    this.SysRegIntf = SysRegIntf;

    walks = new(); 

endfunction 

function void sample ();

    walks.sample(); 

endfunction   

endclass 

In this case, bin values are not static and vary depending on Tag bits in the interface. Is this allowed in system verilog?. It compiles well but the bin values are fozen to 31 - 0 = 30 for MAX and 31 - 0 + 1 to 32 to MAX_PLUS_ONE.  

 

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  • TAM1
    TAM1 over 13 years ago

    The ranges in a bin declaration need to be compile-time constants. Since SysRegIntf is a virtual interface, it can be assigned during run time. So I'm really surprised that this code even compiled. I think it should have been rejected. Here's one way to accomplish your goal.

    class mem_cov_grp;
      virtual SysRegIntf vintf;
     
      logic max_addr, max_addr_1;
      covergroup walks;
        level: coverpoint {max_addr_1,max_addr} {
                   bins MAX = {2'b01};
                   bins MAX_PLUS_ONE = {2'b10};
               } 
      endgroup

      function new (virtual SysRegIntf vintf);
        this.vintf = vintf;
        walks = new();
      endfunction

      function void sample ();
        max_addr   = (vintf.Addr==(31-vintf.Tag));
        max_addr_1 = (vintf.Addr==(31-vintf.Tag+1));
        walks.sample();
      endfunction  

    endclass

    Using this, Tag does not have to be a compile-time constant but different interfaces can have different tags and the bins will be selected appropriately.

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