Stats

  • Locked Locked
  • Replies 5
  • Subscribers 66
  • Views 25606
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

ncverilog simulation verilog: error fmuk

weebey

Hi,

I am trying to run a simulation on my schematic using NC-Verilog in Virtuoso. When I click simuate, I keep getting these errors:

irun: *E,FMUK: The type of the file (/counter_run1/testfixture.template) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds0/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds1/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds2/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds3/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds4/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds5/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds6/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds7/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds8/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds9/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds10/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds11/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds12/netlist) could not be determined.

irun: *E,FMUK: The type of the file (ihnl/cds13/netlist) could not be determined.

 

Does anyone know how to fix this? Thanks. 

  • Add '-sv' to your command line options.

    Tim

  • Thanks for the reply, Tim. I actually ended up fixing this problem with the command -default_ext verilog. However, now I am getting error messages like this one:

     nfetx  M1 ( .S(cds_globals.gnd_), .G(net11), .D(Y),

            |

    ncelab: *E,CUVMUR (./ihnl/cds0/netlist,18|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M1' of design unit 'nfetx' is unresolved in 'worklib.AND2X1:verilog'.

    ncelab: *E,CUVMUR (./ihnl/cds0/netlist,18|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M1' of design unit 'nfetx' is unresolved in 'worklib.AND2X1:verilog'.

    nfetx  M2 ( .S(cds_globals.gnd_), .G(B), .D(hnet14),

            |

    ncelab: *E,CUVMUR (./ihnl/cds0/netlist,20|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M2' of design unit 'nfetx' is unresolved in 'worklib.AND2X1:verilog'.

     Do you know what's going on here? I synthesized the design with Design Compiler and then imported it into Virtuoso as a schematic. 

  • Looks like you need to refer to a cell library that needs to be included on the command line.

    Tim
  • Can I also do this through the gui in Virtuoso? If not, could you explain what I need to do, assuming I know where the library is?

  • I was able to do the following without any errors:

    ncxlmode counter_synth.v -v ibm18.v 

    where counter_synth.v is the netlist to be simulated and ibm18.v is the verilog file for my standard cells. However, I can not figure out how to do this with NC-Verilog within the virtuoso GUI still.

     

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.