Stats

  • Locked Locked
  • Replies 0
  • Subscribers 65
  • Views 12875
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to apply Dynamic Load and Reseed Methodology into UVM

clacasse

I have found some application notes that provide guidance on how to use the Dynamic Load and Reseed Methodology with e/Specman.  Is there an application note or other guidance on how to perform Dynamic Loading and Reseeding using a System Verilog UVM environment?

 

Thank you,

Chris 

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.