Looking for help with System Verilog in AMS

I've generated a netlist for a testcase and get the following error in the irun.log:

Elaborating the design hierarchy:

bias i_bias ( .ibias(ibias[3:0]), .vdd(vdd), .vss(vss), .en(en[0]));

                                         |

ncelab: *E,CUINFI (./netlist.vams,39|41): An interface declaration must be connected to an interface (test_top.i_top).

   Analog vdd, vss;

            |

ncelab: *E,CUIMBC (./development/SYS_VLOG_ANA_TEST/bias_verilog.sv,42|12): An interface port declaration must be connected (test_top.i_top.i_bias).

bias i_bias ( .ibias(ibias[3:0]), .vdd(vdd), .vss(vss), .en(en[0]));

                                                    |

ncelab: *E,CUINFI (./netlist.vams,39|52): An interface declaration must be connected to an interface (test_top.i_top).

   Analog vdd, vss;

                 |

ncelab: *E,CUIMBC (./development/SYS_VLOG_ANA_TEST/bias_verilog.sv,42|17): An interface port declaration must be connected (test_top.i_top.i_bias). 

That goes on for a while and there are a number of them.  So, the question is how do I connect the port declaration?  Here's the file referenced:

 import ADMS_signals_pkg::*;

module bias (

              vdd,

              vss,

              en,

              ibias

             );

`include "parameters.svh"

   Analog vdd, vss;

   Analog ibias[3:0];

   input wire en;

   Amps                 iout[3:0];

   integer              vdd_ok;

   integer              vss_ok;

   integer              supplies_ok;

   event                started;

//   Driver vdd_d         = new(vdd);

//   Driver vss_d         = new(vss);

   ISource ibias_src[3:0];

   initial begin

      foreach (ibias_src[i]) 

        begin

           ibias_src[i]=new(ibias[i]);

        end

      @(en == 1'b1 && supplies_ok == TRUE);

      #100 -> started;

   end

//   Driver ibias_d = new(ibias[1]);

//   Driver ibias_d = new(ibias[2]);

//   Driver ibias_d = new(ibias[3]);

   always @(vdd.changed)

     begin

        if (vdd.v < VDD_MIN)

          vdd_ok = FALSE;

        else if (vdd.v > VDD_MAX)

          vdd_ok = FALSE;

        else

          vdd_ok = TRUE;

     end

   always @(vss.changed)

     begin

        if (vss.v < VSS_MIN)

          vss_ok = FALSE;

        else if (vss.v > VSS_MAX)

          vss_ok = FALSE;

        else

          vss_ok = TRUE;

     end

   always @(vdd_ok, vss_ok)

     begin

        if (vdd_ok == TRUE && vss_ok == TRUE)

          supplies_ok = TRUE;

        else

          supplies_ok = FALSE;

     end

   initial iout[0] = -IBIAS_TYP;

   initial iout[1] = -IBIAS_TYP;

   initial iout[2] = -IBIAS_TYP;

   initial iout[3] = -IBIAS_TYP;

   always @(started,en)

     begin

        foreach (ibias_src[i])

          if ( en==1'b1 && supplies_ok==TRUE)     

            ibias_src[i].seti(iout[i]);

          else

            ibias_src[i].seti(0.0);

     end

endmodule // bias