• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. irun: design.v is verilog and verilog AMS

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 65
  • Views 15577
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

irun: design.v is verilog and verilog AMS

moogyd
moogyd over 12 years ago

Hi,

We are migrating to an irun based flow to simplifiy our compile/elab/sim flow, and have a slight issue.

We have a file design.v, containing module design. Depending on a define, this can either be a standard digital module, or a WREAL model.

i.e. Within the file

`ifdef WREAL

wreal sig_name;

 `endif

This issue is that irun uses the file extesion to infer the type of file, in this case, it does not work.

This is a non-trivial design, so I have multiple verilog, vhdl and vams files, and using the -ams is probably not an option.

Question is: Can anyone suggest a solution? Is there an command line option that I missed, which applies to a single file only?

Thaks,

Steven

 

  • Cancel
  • tpylant
    tpylant over 12 years ago
    A few thoughts:

    1. Rename the file with a “.vams” extension. Since Verilog-2001 is a subset  of Verilog-AMS, the syntax should compile correctly whether you have the WREAL defined or not.
    2. If for some reason you can’t rename the file or you use SV in the non-wreal code, then you could use a unique filename extension (eg. .sv-vams) and then use “=amsvlog_ext +,.sv-vams” for when you define WREAL or “-sysv_ext +,.sv-vams” for when you don’t define WREAL.
    3. If neither of those work, you could just compile the one file by itself and use the “-ams” switch when you define WREAL and then compile the remaining files using your standard irun command.

    Tim
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • moogyd
    moogyd over 12 years ago

    Hi Tim,

    Thanks for the ideas

    1) This would solve the immediate issue. We are currently not using SV, but will be in future. However, I guess that we would not be mixing wreal and sv in the same file.

    2) Extra marks for "thinking outside the box", but no thanks :-) I don't think this solution would make me very popular within the company.

    3) I had thought of this, but we would then start losing irun advantages.

    One more thought I had is to use a verilog pre-processor+Makefile to auto-generate design.vams from design.v

    For now, I'll go with (1)

    Thanks again for the feedback.

    Steven

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information