I've been exploring with the labs in UVM-SystemVerilog Workshop. The lab 1 to 5 are good, but lab 6 is sort of useless. It only shows me how to view the prewritten sessions and vplan. In the end, I don't know how to create the vPlan map the plan to the testbench so that it can automatically measure my verification progress.
I don't why the lab 6 isn't built up from lab 5 which it should.
Is there any other lab/document that I can follow?
I search all over the earth and understand roughly that : you have a spec, then you create your vplan. Your vplan can map to your spec and your vplan can map to your testbench to measure the progress of your verification. I just don't know how to "connect" vplan to my testbench.
Thanks a lot for reading
Thanks for the feedback on the labs. I think the UVM ones try not to distract you too much from the core UVM content, which is why the final MDV section is quite thin. However the SoC Verification Kit shipped with Incisive does have a lot more workshops. If you take a peek at the dedicated MDV workshops you should find a much more detailed set of labs for building your own vPlan, based on the same design.
I'm not sure how you navigated to the contect for the UVM workshop but assuming no prior knowledge of the tools...
Open "cdnshelp" from the Linux prompt, then search for "MDV Planning Workshop". Alternatively open the "Incisive Verification Kits" chapter in cdnshelp's hierarchy pane, then go into "Getting Started" followed by "Kit Workshop Content".
Hope that helps, and please do give us more feedback :)