I've been exploring with the labs in UVM-SystemVerilog Workshop. The lab 1 to 5 are good, but lab 6 is sort of useless. It only shows me how to view the prewritten sessions and vplan. In the end, I don't know how to create the vPlan map the plan to the testbench so that it can automatically measure my verification progress.
I don't why the lab 6 isn't built up from lab 5 which it should.
Is there any other lab/document that I can follow?
I search all over the earth and understand roughly that : you have a spec, then you create your vplan. Your vplan can map to your spec and your vplan can map to your testbench to measure the progress of your verification. I just don't know how to "connect" vplan to my testbench.
Thanks a lot for reading
Jeff, no such thing as a dumb question! :-)
Unfortunately your pictures didn't come through so I can't tell what the problem is. You might try asking your local Cadence AE to help get you started (I'm not sure where you are because you didn't fill in your profile).
There are some introductory videos in the Kit. Navigate in cdnshelp to "Incisive Verification Kits - Getting Started". Under there you have "Kit Workshop Content" followed by "Video Content". These will require you to have Flash player enabled on your Linux machine, or you can access the same docs on your PC via the Cadence web site http://support.cadence.com/.
Specifically you want the Metric Drivern Verification video, this will talk you through all the concepts.
Hope this helps.