I've been exploring with the labs in UVM-SystemVerilog Workshop. The lab 1 to 5 are good, but lab 6 is sort of useless. It only shows me how to view the prewritten sessions and vplan. In the end, I don't know how to create the vPlan map the plan to the testbench so that it can automatically measure my verification progress.
I don't why the lab 6 isn't built up from lab 5 which it should.
Is there any other lab/document that I can follow?
I search all over the earth and understand roughly that : you have a spec, then you create your vplan. Your vplan can map to your spec and your vplan can map to your testbench to measure the progress of your verification. I just don't know how to "connect" vplan to my testbench.
Thanks a lot for reading
Please send me an email to email@example.com with your screenshots. We'll see if we can help you further.
The workshop is the best place to get started but you'll need to make sure you follow all the setup instructions it mentions.