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string macros in verilog AMS

freitas
Hello, 
Does anyone know how to define string  macros in Verilogams?
 
Today I have to do the following:
`define display_value(str, sig)  $display(“Value of signal %s is equal to %b”,  str, sig)
 If I place the following macro in my code
`display_value(“mysignal”,mysignal);
 The compiler translates to
$display(“Value of signal %s is equal to %b”,  “mysignal”, mysignal);
 Unfortunately, it forces me to duplicate information and maintain more code.
 Ideally I would like a macro that takes a single argument to create the signal name as well as its respective content.  Such as:
`define display_value(sig)     ????????????????
I wonder if there's a trick in verilogams to accomplish that. 
Any ideas?
Thanks,
Art. 

  • Dear all,

    I have the same problem.

    this solution does not work

    `define display_value(str)  $display(“Value of signal %s is equal to %b”,  `"str`", sig)

    neither this solution

    `define display_value(str)  $display(“Value of signal %s is equal to %b”,  `" \str `", sig)

    or this

    `define display_value(str)  $display(“Value of signal %s is equal to %b”,  \" str \", sig)

     

    In systemverilog this is easily done, but what about in verilogAMS ?

    is there a way to use the input argument of a verilogAMS macro as a string with "" ?

     

    Thank you

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