Stats

  • Locked Locked
  • Replies 0
  • Subscribers 65
  • Views 13030
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Continue after failed PSL assertions

wltr

Hi!

I am running a mixed-language simulation with irun. This includes PSL assertions in my VHDL code and SVA assertions in my SystemVerilog/UVM testbench.

As the simulation runs in non-interactive mode on a cluster, I do not want the simulation to stop due to failed assertions. It rather should log it in the database and continue.

But the simulation already stops on the first failed assertion. I was not able to find any configuration flag to force ncsim to continue automatically.

Any hints would be highly appreciated.

- Johannes 

 

EDIT: Okay, sorry. I just found the problem. My own script prevented the simulation from continuing.  

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.