I am new to the formal verification process and I am trying to use it for verifying the connectivity between some modules in a SoC. I am using Incisive Formal SoC Connectivity Solution (V2.01) speadsheet to create the property file for the specified connections.
While verifying the connections I am finding certian issues:
1. The connection status is passed and the connection is visible in schematic but when I view waveform for the same, I get only 0 is driven on both the pins. How can I assure that the connection is verified if only 0 or only 1 is driven for entire simulation cycle? Is there any way to toggle the input on pins with the help of connectivity spreadsheet?
2. When the top file language is specified as verilog in the excel sheet, then the property file created by using the CSV file contains a clock, ifv_connectivity_clk. Where does this clock comes from? I have not specified any such clock in the spreadsheet. At the same time when the top file language is changed to vhdl, no such clock is generated. Why is this so?
I am using PSL assertion language in the excel sheet.
Got this doubt cleared. The sarch command will never show a pass result it will always show explored for the assertions that are passing. This is because search command runs a simulation .It will not run exhausively. We need to issue prove command to thorougly verify the design.
Thanks a lot for help.