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IVB not supporting additional port definations for systemverilog UVC creation

pravintavagad

I am trying build UVC using IVB but IVB not showing Port definations dialog for Systemverilog-UVM where as it is showing it for UVM-e.

Please help me to declare additional ports in IVB.

 

  • Hi,
    you can just add your ports to the interface definition. The file is called <your_package>_if.sv in the sv directory. Once the ports are there, they can be accessed via the interface pointer in various components (e.g. vif in the driver).
    Regards,
    -hannes

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