Creating e Wrapper for system verilog code

 Hi all,

    I am try to creating eRM Wrapper for  sv Environment. In that environment systemverilog tasks/function which is called from specman e methods. I have better knowledge in both Verification component. but i need how to interfere this both Verification component. if any body have an Idea about this. share your knowledge this will helpful for me to update

example code:

In Sv:

    function void m(bit [`ADDR_SIZE-1:0] addr,bit [`DATA_SIZE-1:0] data);

    $display("ADDR: %d",addr);
    $display("DATA: %d",data);
    $display("iam here");
    endfunction

In eVC:

 .......here, how can i call above systemverilog function ?....

Thanks & Bestregards,

selvavinayakam.na