While running an IFV assertion check, the trace and trigger are showing the status "Pass" whereas the result is shown as "Fail".
Please tell me where the issue could be?
Hi, it seems the failure came from design itself. Please open CEX of the failed assertion and is should be able to show you why assertion failed. You can then debug the RTL logic accordingly.
Trace and Trigger pass means that the tool was able to find at least one way to trigger the check and to complete the check. Basically these are coverage, telling you that the assertion hasn't passed vacuously.
It's perfectly natural to have trace and trigger passing with a failing assertion, you should only worry about these if you get an assertion pass when the trigger or trace are failing.