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Gate Level Sim - SDF annotation debug

andymont

Hi, 

I am trying to annotate an SDF to my gate level synthesis netlist and I am seeing some strange behaviour.

When I annotate using just the netlist, cell_lib and sdf , everything works fine. However, when I try to annotate using the testbench and providing the full scope to the netlist within the verification environment (SCOPE=test_env.<scopetodigtop>.udig_top), I see thousands of 

SDFNEP, SDFNET errors. The paths and timing checks which ncelab is complaining about definitely do exist in the cell_lib verilog, and the scope is definitely correct. I have tried modifying the scope just to make sure that it was correct and with anything apart from these settings the annotator complains that the scope is incorrect and refuses to proceed.

What am I missing and what is the best way to debug this ?

I have tried versions incisiv/11.10.011, incisiv/12.10.011 and incisiv/12.20.008 

thanks

Andy 

Parents
  • Found the issue. My run script had inherited a '-delay_mode unit' switch which for some reason meant that Incisiv knew nothing about the timing checks. The warnings make sense when you know the solution but they're not very helpful during debug. Problem solved! Andy
Reply
  • Found the issue. My run script had inherited a '-delay_mode unit' switch which for some reason meant that Incisiv knew nothing about the timing checks. The warnings make sense when you know the solution but they're not very helpful during debug. Problem solved! Andy
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