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Getting vhdl constants in system verilog

rajay

Hi,

 I need to re-use the constants and record type variables  in system verilog which are defined in vhdl DUT (in a separate package file). I could not find the idle way to do this task except rewriting the constants in systemverilog again with some manual work. I tried with import statement but didnt work. I was not sure whether i need to add any extra command line arguments to do this. Could any one please shed a light on this?

 

Thanks for your time.

 

Regards,

raja 

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