I need to re-use the constants and record type variables in system verilog which are defined in vhdl DUT (in a separate package file). I could not find the idle way to do this task except rewriting the constants in systemverilog again with some manual work. I tried with import statement but didnt work. I was not sure whether i need to add any extra command line arguments to do this. Could any one please shed a light on this?
Thanks for your time.
This isn't something which is supported in the current simulator version. We do however have a tool to make type conversions.
If you PM me with your company email address, I can help you.
Thanks Steve for the update. You can send me details to firstname.lastname@example.org.