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which all signals need to be initialized in a module

BharathECE

Hi

 Iam doing formal verification,Iam getting so many signals unitialized.Iam not understanding which signals we should initialize.How to know which signals we should initialize in a module.

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  • BharathECE,

    This is not a formal only question.  What does the designer or spec say about resetting the design?  If you are running simulation you have the same concerns.

    To initialize the design in IEV, use the tcl force commands to drive the reset signals to their appropriate values and then use the run command to run the clocks.

    clock -add clk 

    force reset_n 0
    # Run the reset for 5 clocks
    run 10
    # Load formal model with initialization state
    init -load -current
    # Display flop values
    init -show

    Hope this helps jumpstart you.

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  • BharathECE,

    This is not a formal only question.  What does the designer or spec say about resetting the design?  If you are running simulation you have the same concerns.

    To initialize the design in IEV, use the tcl force commands to drive the reset signals to their appropriate values and then use the run command to run the clocks.

    clock -add clk 

    force reset_n 0
    # Run the reset for 5 clocks
    run 10
    # Load formal model with initialization state
    init -load -current
    # Display flop values
    init -show

    Hope this helps jumpstart you.

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