Iam doing formal verification,Iam getting so many signals unitialized.Iam not understanding which signals we should initialize.How to know which signals we should initialize in a module.
Thanks for the reply,
Its true this question was nothing related to IFV.Actually in any design we need to have some signals initialized as per design after reset process completed.
That we can do by doing signal force. These things need to be discussed with designer of particular block/module.