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AFA for VHDL in IFV

Buvna over 12 years ago

Hey,

I have mixed language in my design (Verilog and VHDL).

I notice that AFA is generated only for Verilog and not VHDL. Is this a problem with the tool?

Thanks.

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JoergM over 12 years ago

Hi,
IFV support AFA in all HDL languages including VHDL, Verilog and SystemVerilog. What you experience is either a setup or a tool problem.
Jörg.
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JoergM over 12 years ago

Hi,
IFV support AFA in all HDL languages including VHDL, Verilog and SystemVerilog. What you experience is either a setup or a tool problem.
Jörg.
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