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Formal Verification with SystemVerilog and ifv

m123

Hi,

i am trying to verify some SystemVerilogAssertions of a SV implementated communication network with incisif formal verifier, but the verification process takes a very long time and the computer crashes after 20 hours. The assertions test the whole network of sending and receiving. So is it possible to reduce the duration with some special commands (i use auto_dist as engine) or is the complexity an almost unsolveable problem?

 

  • Hi,

     Complexity can often be addressed with methodology and tool capabilities. But this is a large topic that will be difficult to discuss using this forum. I can suggest a couple of things

    1) view an older post in which document was posted on how to improve performance

    /forums/T/26285.aspx 

    2) discuss with your local AE

     Thanks,

    Chris 

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