Stats

  • Locked Locked
  • Replies 1
  • Subscribers 65
  • Views 13516
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

CMOS INVERTER LAYOUT DEBUG!?

tempVar

 Hello all. So I am in the process of simulating my layout extraction. I ran DRC which was successful.I ran LVS which returned a negative output (my schematic netlist and extracted netlist DO NOT MATCH);however, I continued with the simulation hoping to see if I can gain some info from the plots... 

 Here is my layout and the plot of the simulation of the extraction (sorry for the bad quality layout image). 

Please help me debug this issue. What should I be looking for?

 Thank you.simulationLAYOUT

  • Fixed! It is kind of obvious where the problem is! If you can tell the nmos seems to be working properly (as seen in the wave forms). It is the pmos part that seems to be messed up, it is also apperent that the pmos is simply not doing anything or in other words; not functioning... Hmmmm, what may cause such an issue? THINK ABOUT IT!!!

     Done thinking?

     I didn't have a voltage source for my pmos! : ( 

    Sorry for the premature thread, next time I will give it more thought. I have 93 views as of this writing though, I bet you guys are also working on the same assignment I am... Good luck!

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.