One question about system verilog `__LINE__ define

 There is a compiler derective in system verilog -- `__LINE__, it will expands to the current input line number. But I find it will return current line number -1.

For example, in below code(the left is line number):

1 initial begin
2 signal_a = 0;
3 signal_b = 1;
4 $display("current line is: %0d",`__LINE__);
5 end

When I run this code using ncsim, it will output:

current line is: 3

It's so strange, I think it should output "current line is: 4", because obviously this line number is 4, but not 3.

Can somebody tell me why?
Thanks a lot!