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Error on CLSMIP

DesignVerif

Hi

I am new to UVM and I am getting following error.

  Can anybody please help me out

  my_sequencer#(my_trans) sequencer

  ncvlog: *E,CLSMIP (./sv/my_agent.sv,25|34): Too many class instance parameter assignments. 

Thanks in advance 

  • Assuming you are trying to define the sequencer handle, it should be:

        my_sequencer sequencer;

  • Thanks it did work But for understanding , does it tell that my_trans is transaction being used in my_sequencer. Also in some example I found out that syntax is given as below. my_sequencer#(my_trans) sequencer Can you please do let me whats the difference between above declaration and my_sequencer sequencer declaration

  •  When you define your component like this:

        class mysequencer #(type X=int, Y=real) extends uvm_sequencer #(myobj);
        ...

    It means that your object or component is parameterized. In this case you will create a handle like this:

         mysequencer #(int,string) foo = new(); 

    You provide a type parameter for X and Y. Not myobj.

    When you extend your component like this:

        class mycomp extends uvm_sequencer #(myobj)

    It gives you a built in handle called "req" which you can use for referring to your transaction object. #(myobj) is the type parameterization for the transaction.

    I hope this is clear.

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