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  3. UVM Sequence

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UVM Sequence

DesignVerif
DesignVerif over 11 years ago

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  • Tudor Timi
    Tudor Timi over 11 years ago

    What you did here is constrain all 3 transactions to have exactly the same values for ch_sel, mod_sel and adstt. The way it works is that you have your value of c_ch_sel declared as a field in the sequence (I guess, since you don't show it). This gets randomized when the sequence is started and keeps its value. Afterwards you say that all your items that you start should have their ch_sel equal to c_ch_sel. If you want them to have different values for the 3 fields do this:

    virtual task body();

        repeat(3) begin

            `uvm_do(req)
        end       
    endtask 
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  • DesignVerif
    DesignVerif over 11 years ago
    yes
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  • Tudor Timi
    Tudor Timi over 11 years ago
    Not really sure what you mean. If you do what you showed you'll just override the body() of your base sequence with that of your derived sequence. What is it exactly that your trying to achieve (in plain words, not code)?
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  • DesignVerif
    DesignVerif over 11 years ago

     

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