Stats

  • Locked Locked
  • Replies 1
  • Subscribers 65
  • Views 13429
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Passing parameters form verilog to systemC

jbriquet

Hello,

I want to call a systemC function in a Verilog shell using a wrapper, and I want to pass parameters from verilog to systemC, using "ncsc_get_param" in systemc side.

But I have a problem, because it is necessary to put parameters in the verilog wrapper, whereas I want to put them in a higher hierarchy ...

Please tell me if that i want is possible or not ?

Sincerely , jean-Pierre 


  • I have also noticed when I simulate only verilog wrapper and systemc module, I can see parameters on the schematic, but when I add a systemVerilog shell which calls the wrapper, parameters dissapears .... I think there is a kind of mask on the systemc module ... Can someone explain me this bthing . Thank you very much 

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.