Bind SVA to VHDL Enumerated Type

Hi,

I’m writing SystemVerilog assertions to check a VHDL state machine, and I need to bind the assertions to the VHDL component. What is unclear is how should I write the module port list? For example, the assertion should looks something like this:
 
property p_state_chk;

  @(posedge clk)

    state == ST2 |-> $past(state,1) == ST1;

endproperty
 

The signal state is defined as an enumerated state in the VHDL source, similar to the following:
 

type state_type is (ST1, ST2, ST3);

  -- signal declarations

  signal state   : state_type;
 I've declared a port in the assertion module similar to the following: package enum_pkg;
  typedef enum {ST1,ST2,ST3} smpl_st_t;
endpackage module comp_chk (clk,state);  input clk;
  input enum_pkg::smpl_st_t state;endmodule The binding is accomplished like this: bind comp comp_chk u_comp_chk (.clk(clk),.state(state));

However, I continue to get elaboration errors (E,CFMPTC). How can I bind the above assertion to the VHDL enumerated type? Is the enumerated type in the assertion module defined as a string, and bound to the VHDL component? Is using $nc_mirror an option?

Thanks,

Tony