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  3. In UVM is there any Inheritance like "Specman e when Inheritance...

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In UVM is there any Inheritance like "Specman e when Inheritance"..

Selvavinayak
Selvavinayak over 11 years ago

Hi all,

I need following Information,

In Specman e: 

  we are able to Create field  inside the struct like

sample Code:

when WRITE'trans_type

{

  addr: uint[31:0];

};
 

when READ'trans_type

{

  addr: uint[8:0];

};
 

In UVM:

  If I want to create a field in parent Class using Inheritance is Possible... I have Better Knowledge in Spceman e. I am new to UVM due to comparing those Environment feature I got this Doubt...

 

Please any body Share your Knowledge to Update myself... 

 

Thanks,

Selvavinayakam.na

 

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  • Tudor Timi
    Tudor Timi over 11 years ago
    To the extent of my knowledge, 'when' inheritance is unique to e. SystemVerilog only supports 'like' inheritance.
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