Functional Coverage Question

I assume this is SystemVerilog. For ignore bins in cross coverage have a look at this site:

 http://www.asic-world.com/systemverilog/coverage20.html 

Can you give us a more concrete example? I don't understand what you mean by auto bins, since as soon as you define your own bins the tool won't create auto bins in the coverpoints.

Inside the cross, you can get rid of the auto bins by using the Incisive coverage control command: "set_covergroup -cross_auto_bin_max_default_zero" which needs to go in the coverage control file, passed to irun or ncelab via the -covfile option.

Here's a small example adapted from the LRM, maybe you can tweak it to show us what you're seeing? In Incisive 13.20 this runs and does not produce any auto bins.

module test;
bit [7:0] v_a, v_b;
event clk;
covergroup cg @(clk);
  a: coverpoint v_a {
    bins a1 = { [0:63] };
    bins a2 = { [64:127] };
  }
  b: coverpoint v_b {
    bins b1 = {0};
    bins b2 = { [1:84] };
  }
  c : cross a,b {
    bins c1 = binsof(a.a1) || binsof(b.b1);
    bins c2 = binsof(a.a2) || binsof(b.b2);
  }
endgroup

cg cgi;

initial
begin
  cgi = new;
  for(v_a=0; v_a<255; v_a++)
    for (v_b=0; v_b<255; v_b++)
    begin
      #1 ->clk;
    end
end

endmodule