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UVC Source Synchronous Interface

rlanier

I am attempting to develop a UVC with a source synchronous interface. I need to be able to control the flow of clock and data to the DUT such that when requested, the clock and data are gated off (essentially, the interface is disabled).

Controlling the flow of data is relatively straight-forward. Where I'm getting wrapped around the axel is with the clock. How can I drive the clock from the driver such that is can gated off/on?

  • It might be simplest to add an ancilliary clock enable signal to the UVC's interface so that you can have a free-running clock into the UVC to allow cycle-based delay timing. You'd then externally gate the clock in the test harness before it goes to the DUT.

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