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Uninitialized Clock Gate Cells

When simulating a netlist containing integrated clock gate cells (icg), we have many of these cells that propagate unknown states ('x') due to the fact that the clock signal is initialized high and the latch in the clock gate cell is uninitialized. This causes problems during sim startup.

I was wondering if there is a common technique for dealing with this situation. Do you perform a 'force' to initialize all of the icg latches? Or is there some other technique that you prefer.

Thanks in advance for any advice!

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