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Error in Elaboration in UVM environment

sunil kr

I am trying to test the VHDL DUT in UVM environment and as i can see using the libverbose all the units are properly resolved when i used irun and it shows error in elaboration as below :

irun: *E,ELBERR: Error during elaboration (status 1), exiting.

I am not able to see any other error messages.

Can you please help me how i can further debug to know the exact reason for the error ? 

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  • sunil kr
    If i remove the coverage related files then i am able to resolve the issue. Thanks
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  • sunil kr
    If i remove the coverage related files then i am able to resolve the issue. Thanks
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