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Back annotating the SDF data to a verilog nestlist in VHDL testbench

Dear experts

I am using VHDL as description language for my RTL development including testbenches and Cadence RC for synthesis. The synthesized netlist is in veilog and I would like to use it within the VHDL testbench to perform GLS. The standard cell models are available in verilog as well. I want to back annotate the timing information in SDF file generated during synthesis. Could someone guide me on the steps to be followed for the same. I use ncsim for simulation environment.

Thanks and regards

Venkat

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