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  3. UVM_ML (SystemC + SystemVerilog TB)

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UVM_ML (SystemC + SystemVerilog TB)

vitok
vitok over 10 years ago

Hi,

Question about architecture of SystemC UVM  + SystemVerilog UVM.
Can those two approaches be mixed?

1. Can SystemC uvm_components exist within SystemVerilog's UVM tree hierarchy?
  In other words - can SystemVerilog instantiate SystemC class in itself?

2. If SystemVerilog UVM cannot instantiate in itself UVM components of SYstemC - it will mean that the testbench will have multiple tops (one top for SC, the other for SV), is it correct?

Many thanks

Witold Kaczurba

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  • hannes
    hannes over 10 years ago

    Hi Witold,

    My answers are with respect to the latest multi-language solution, UVM ML-OA, which is available here:
    http://forums.accellera.org/files/file/65-uvm-ml-open-architecture

    U
    sing the above package (which also has detailed documentation), the answer to your question 1 is yes, you can create
    a mixed language hierarchy. However, you cna also have multiple tops (question 2) if this is what you prefer.

    Regards,
    -hannes

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  • vitok
    vitok over 10 years ago

    Hi hannes


    Perfect. I saw the example here:

    in UVM_ML-1.4.4/ml/examples/unified_hierarchy/sc_sv

    I did not get a chance to run it yet as I encountered some issues with installation of the package (hopefully solvable soon.)

    Thanks for your email.

    Rgds,

    Witold

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  • vitok
    vitok over 10 years ago
    All working thanks.
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