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Parameter Configuration-UVM help!!

Nhatt

Hi everyone

I'm a newbie on UVM verification, I'm building a environment to verify my design. In my design It has a clock input whose the clock frequency can change from user. I intend to test the design with with different clock frequency. How can I configure this? 

Please have a look at my testbench top

module wdt_top_tb;

// `include "uvm_macros.svh"
parameter cycle_1 = 15.625;
parameter cycle_2 = 20;

//Interface declaration
wdt_if vif();
wdt_clock_mux_if wdt_clk_mux_if0();

//Connects the Interface to the DUT
wt_top dut(vif.clk1,
vif.clk2,
vif.rst_b,

...)

How can I change the cycle_2 parameter with the configuration from testcase?

Thank you!

Parents

  • Hello.

    You cannot change a parameter procedurally, because parameters are fixed at elaboration time. You could replace it with a variable instead. However you should consider using the Cadence clock and reset package for this task, it has a really good structure for controlling clocks and resets (!) from UVM sequences. Best of all, it's designed to perform well in large environments and even if you move over to an accelerated testbench setup where your DUT goes onto an emulator you won't have to make code changes to get optimal performance.

    You can find the clock and reset package in our testbench accelleration rapid adoption kit, here:

    Specifically you need the one title "Developing a single environment for software simulation and hardware acceleration"

Reply

  • Hello.

    You cannot change a parameter procedurally, because parameters are fixed at elaboration time. You could replace it with a variable instead. However you should consider using the Cadence clock and reset package for this task, it has a really good structure for controlling clocks and resets (!) from UVM sequences. Best of all, it's designed to perform well in large environments and even if you move over to an accelerated testbench setup where your DUT goes onto an emulator you won't have to make code changes to get optimal performance.

    You can find the clock and reset package in our testbench accelleration rapid adoption kit, here:

    Specifically you need the one title "Developing a single environment for software simulation and hardware acceleration"

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