VHDL sensitivity list checking in Incisive

Hi Dave.

ncvhdl is just a parser and doesn't do any higher-level checking of your code (i.e. it cares that the syntax is correct, but doesn't understand your intent).

What you want is the HAL (HDL Analysis and Lint) tool which comes as part of Incisive.

To use HAL either get your design compiled to a simulation snapshot with ncvhdl and ncelab, ensuring that it's elaborated with "-access +rwc" to permit HAL to see into the design structure, then run "hal <snapshot_name>". This runs all the RTL lint rules including one for incmplete sensitivity lists (inferred latches).

You may prefer to move off the old ncvhdl / ncelab / ncsim flow, and use the more current "irun" command which is a one-stop tool for running all the flows. Its use model is simple:
irun *.vhd *.v

It also accepts most ncvhdl, ncvlog, ncelab and ncsim arguments. By default it compiles, elaborates and simulates all in one.
You can get it to stop after elaboration with the -elaborate option, then simulate with "irun -R" to run whatever you just compiled.
You can also do things like:
irun *.vhd -hal

Hope this helps.

Steve.