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Need help in Verilog file creation

I have a file which is extended to .tdf (Text Design File) from altera library. I want to convert it to traditional verilog code.

Can anyone help in this regard?

thanks,

mahee

mahee424 over 9 years ago

Hi,

The conversion from TDF to verilog has been done with the script supported by altera. This is not the place to share the above query b'cse this is not relevant to verification flow.

regards,

mahee
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