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Transition model of the hardware design by Cadence IFV

Hello,

I wanted to know how the transition system of the hardware design is extracted from the Verilog code of the system by the Cadence IFV tool.

As far as I know, model checking tools synthesize the RTL code written in Verilog or VHDL and then use model checking algorithms to perform verification against formal specifications. Does Cadence IFV follow the same process ?

StephenH over 9 years ago

Yes, it effectively synthesises the RTL, to a boolean model. That is all done internally to the tool though, as a user you still interact with the RTL and the results are always shown against the RTL.
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RAJGD over 9 years ago

Thank you Stephen. Yes, I have been using IFV and have been working with the HDL codes and assertions. But, I wanted to know the internal working of the tool. Thank you again for the information.
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