• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. Simulation in NCSIM

Stats

  • Locked Locked
  • Replies 1
  • Subscribers 65
  • Views 14110
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Simulation in NCSIM

Eliz
Eliz over 9 years ago

NCSim simulation  

 

  1. What are the steps to be taken care to perform simulation of PCIe communication in NCSIM for two different FPGA devices?
    1. FPGA 1 device (Kintex Ultrascale) - PCIe(Gen3 x4)  is configured as Root Port
    2. FPGA 2 device (Kintex 7) - PCIe(Gen2 x4) is configured as End Point

The two FPGA devices communicates via PCIe.

 Root port and End port are configured using Vivado and Scripts are genertaed for ies from Vivado.

 

  • Cancel
  • StephenH
    StephenH over 9 years ago

    Hello Elizabeth.

    Are you simulating RTL? If so, then it's likely that you can simply compile the two designs simultaneously. The only time it might get more complicated is when you have incompatible libraries from Xilinx for the Xilinx macro cells, e.g. if the PCIe core model is different for the two different FPGA devices. Check with your Xilinx support / documentation though, because the model might not be different. If you do need to compile each FPGA design against different cell libraries, you might need to use the Multi-Snapshot Incremental Elaboration (MSIE) flow, which allows you to perform the compilation and elaboration of each design independently, and then link them together to form a single simulation. It's quite straight forward but it's probably easiest to look at one of our examples such as the MSIE Rapid Adoption Kit (RAK) which is available if you log into our support.cadence.com site.

    Either way, you'll need some kind of test harness code to connect up the PICe wires between the two devices, as well as creating all the other stimulus and checkers that you want.

    Obviously simulating two PCIe nodes booting and establishing the link will be quite slow, so you may need to enable the fast simulation link bring-up mode in the Xilinx model. It's a few years since I last ran the Xilinx models myself so I forget the options that are used to make it work.

    I realise there's a limit to how much you can say about your design on a public forum, so if you need more focussed support to get this running, may I suggest that you file a support ticket at support.cadence.com and one of our AE team will contact you to help.

    Regards,
    Steve

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information