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Query regarding the usage of analog assertions in systemverilog file

susanta

Hi Team,

Presently I am developing a test-bench that include assertion checks for some analog signals. But facing some issues as described below.

1. I used the $cds_get_analog_value(hierarchy,"type") to get the value of an object in my design. The syntax I used is

someVar =  $cds_get_analog_value(hierarchy,"type");

But getting compilation error saying "Missing Right parentheses" and the = sign is highlighted in red.

I am not sure if some kind of special license is required to run simulation with the system tasks like $cds_get_analog_valure()/$cds_analog_is_valid() etc. Would someone please give me some clue on this? 

2. I used these system tasks in .sv file. Is it fine? Do I have to use file with extension .va/.vams? But the assert command is not being recognised  in .va/.vams file.

Thanks and Regards

Susanta

  • Is "somevar" defined as a real variable?

    Tim

  • Hi Tim, Thanks for your reply. Yes, someVar is defined as real. Susanta

  • I cannot reproduce your problem. Here is a very simple test:

    test.sv
    module test;
      real somevar;

      top top();

      initial begin
        #1 somevar = $cgav("top.othervar");
        $display("somevar = %2.2f", somevar);
      end
    endmodule

    top.vams
    `include "disciplines.vams"
    module top;
      electrical othervar;
      analog begin
        V(othervar) <+ 2.2;
      end
    endmodule

    amscf.scs
    simulator lang=spectre
    timeDom tran stop= 30us

    amsd {
    ie vsup=5.0
    }

    % irun test.sv top.vams amscf.scs

  • Hi Tim, I tried your code and it worked perfectly fine. But when I changed the electrical branch to wreal variable it's not running. So is there any way to get the $cds_get_analog_value() working with wreal variable? Or it works only with branch and node?
  • I would like to elaborate my previous query. I created a design which has 2 wreal type input ports of the few. Now I created a top level testbench in sv where I tried to get the two wreal type ports values using $cgav() to measure the difference. But I got error. Then I took a real variable in the design file say diff = var1-var2 and tried to get this diff from the sv top using $cgav() and it worked. Is it possible to get some use cases of these system functions along with their limitations? Thanks.

  • From my understanding, the $cgav system task is only available when the analog solver is invoked. Therefore, you wouldn't be able to use it with wreal variables in a non-analog simulation.

    Tim

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