Any alternative way to connect an internal DUT's signals to TB's interface's modport?

Hello,

I have a DUT with a controller and memory inside it - connected via an interface-protocol, say AXI.

Then I have a TB with DUT_inst  & Interface_inst. The purpose of this interface_inst is to monitor the AXI interface to report the wiggling to an UVM component (using virtual interface binding). This interface_inst provides multiple modports for both monitoring + driving purposes.

For connecting the DUT signals to interface_inst, I used MULTIPLE "assign" statements. This is working fine. Now my question is, if there is an easy way to connect the DUT signal to the interface_inst in a single statement, without these multiple assign statements. Something like connecting the DUT signals to interface_inst, while instantiating it in TB itself.

Note:  The controller/memory are legacy verilog modules, which do not have modports on them. They just simply have legacy ports, instead.

Sample code snippet of my scenario is shown below:

/*** CLKGEN module ***/
module my_clkgen (output logic clk);
endmodule

/*** CONTROLLER module ***/
module my_ctrlr (output logic o, input logic i);
endmodule

/*** MEMORY module ***/
module my_mem (output logic o,input logic i);
endmodule

/*** INTERFACE definition ***/
interface my_intf (input clk);
  logic         c_to_m;
  logic         m_to_c;

  modport   ctrlr_modport (input c_to_m, output m_to_c);   // Modport for DUT's controller
  modport   mem_modport (output c_to_m, input m_to_c); // Modport for DUT's memory
  modport   mon_modport (input c_to_m, input m_to_c);    // Modport for passive monitor
endinterface

/*** DUT module = CONTROLLER + MEMORY ***/
module my_dut;
   wire                 c_to_m_net;
   wire                 m_to_c_net;

   my_ctrlr           ctrlr_inst(.o(c_to_m_net) , .i(m_to_c_net)); // CONTROLLER Instance
   my_mem        mem_inst (.i(c_to_m_net) , .o(m_to_c_net)); // MEMORY Instance
endmodule

/*** TB module = DUT + CLKGEN + INTERFACE ***/
module my_tb;
   wire                 clk_net;

   my_dut           dut_inst();                                                          // DUT instance
   my_clkgen     clkgen_inst(.clk(clk_net));                              // CLKGEN instance

   my_intf           intf_inst (.clk(clk_net));                                    // INTERFACE instance
   assign            intf_inst.c_to_m = dut_inst.c_to_m_net;      // Connect DUT signal to Interface
   assign            intf_inst.m_to_c = dut_inst.m_to_c_net;      // Connect DUT signal to Interface

   //my_intf intf_inst (.clk(clk_net),
   // .mon_modport.c_to_m(dut_inst.c_to_m_net),                 //** IS SOMETHING LIKE THIS POSSIBLE **??
   // .mon_modport.m_to_c(dut_inst.m_to_c_net)                  //** IS SOMETHING LIKE THIS POSSIBLE **??
   // );
endmodule

I'm new to SV HDL language. Will really appreciate your quick inputs. Thanks.

-Regards

Kishore