bind procedure doesn't work if target VHDL unit is from a library

I am trying to make a bind between a system verilog module and a vhdl unit which is part of a library and i get the following error: 

example_i : entity work.example(sv) port map (a => score_even(15));
|
ncvhdl_p: *E,SELLIB (...../INCA_libs/irun.lnx86.15.10.nc/.cdssvbind/cds_tmp_svbind000023e3_a20a2600_0x41070b09.sva,3|23): unit (example:sv) not found in library (ana_top_lib).

My code looks like this:

module example(output real a);

endmodule

module top;

dut_wrapper dut_i (

....

)

bind top.dut_i.tb_wrapper_i.dut_top_i.analog_core_u example example_i(
.a(score_even[15])
);

If i try a bind between the same sv module and a vhdl unit which is not in a library then everything is fine. 

Is there any flag that i should use for this kind of binding to work?