Capacitor model SystemVerilog

Hi to everyone, 

I'm working on systemverilog code for my mixed signal IC, to improve the velocity of the simulation. For the resistor and capacitor connected to ground i use the model from cadence, but now i need the model for a capacitor without a pin connected to ground.

to made it i fuse the code of resistor (with P and N terminal) and the code of capacitor connected to ground. the code work and the behavior of component is ok, but not the tension and current value. the code is this:

`timescale 1ns/1ps
import EE_pkg::*;

module  Cap(
inout EEnet P,
inout EEnet N,
input real cval
);


parameter real vtol=1e-6;    // voltage tolerance for iterations.
parameter real rmin=1e-4;    // minimum differential resistance.
parameter real rmax=1e2;    // "off" resistance for Z
parameter real itermax=20;   // max iterations at one timepoint.
parameter real rs=1;        // voltage tolerance for iterations.

real Rval;                        // limited versions of rs inputs
real VPin,RPin,VNin,RNin;              // inputs with small changes ignored
real VPeff,RPeff,VNeff,RNeff;          // effective external V & R values
real VPdrv,RPdrv,VNdrv,RNdrv;          // voltage & resistance output drives
real TPdrv=0,TNdrv=0;                  // time of most recent driver updates
integer iterP=0,iterN=0;               // number iterations at this timepoint


parameter real ic=0;       // initial capacitor voltage at time zero
parameter real tinc=1e-10;  // timestep for computing voltage update (sec)
parameter real itol=1e-7;  // minimum current

real Vcap=ic,Tcap=0,Icap=0; // voltage on capacitor @ time, and current value
real Inew;                  // recomputed current at end of interval
real tinct = tinc*1s;       // tinc converted to timescale units
real Vout,Tout;             // voltage value to output pin (limited update)
reg ck=0;
always #(tinct) ck=!ck;   // toggle clock at defined rate

real Vcapn=ic,Tcapn=0,Icapn=0; // voltage on capacitor @ time, and current value
real Inewn;                  // recomputed current at end of interval


initial begin   // block starts in "off" mode, effective values are as measured:
  VPdrv=0;
  RPdrv=rmax;
  VNdrv=0;
  RNdrv=rmax;
  VPeff=P.V;
  RPeff=P.R;
  VNeff=N.V;
  RNeff=N.R;
end

// update VPin,RPin,VNin,RNin but skip LSB type changes:
always @(P.V,P.R) begin
  if ((abs(P.V-VPin)<1e-14)==1'b0)       VPin=P.V;
  if ((abs(P.R-RPin)<=RPin*1e-14)==1'b0) RPin=P.R;
end
always @(N.V,N.R) begin
  if ((abs(N.V-VNin)<1e-14)==1'b0)       VNin=N.V;
  if ((abs(N.R-RNin)<=RNin*1e-14)==1'b0) RNin=N.R;
end

// update Rval whenever rs change, filtering special cases:
always begin
  if (rs<rmin)       Rval=rmin;      // min resistance
  else if (rs>rmax)  Rval=rmax;      // max resistance
  else                 Rval=rs;      // normal resistance
  @(rs);
end

always begin
  if ($realtime>TPdrv) begin        // new timepoint
    TPdrv=$realtime;                // save time value
    iterP=0;                        // start counter
  end
  else begin
    iterP+=1;                       // else increment counter
    if (iterP==itermax) $display(
     "<EE> ERROR: instance %M node P unconverged at T=%.0fns", $realtime);
  end
  if (iterP<=itermax) begin

          RPeff = RPin*RPdrv/(RPdrv-RPin);
 RNeff = RNin*RNdrv/(RNdrv-RNin);



  Inew = (rs==0)? P.I : (P.V-VPeff)/rs;   // compute new current
  Vcap += (Inew+Icap)/2*($realtime-Tcap)/(cval*1s);  // update voltage by I*dT
  Tcap = $realtime;                      // save time of cap computation
  Icap = Inew;
  if (abs(VPeff-Vcap)>vtol) begin  // if enough dV&dT
    VPeff <= Vcap;                        //  update output voltage
    VNeff <= P.V - Vcap;
  end

        end

    @(P.V, P.R, N.V, N.R, cval, ck);
end


assign P = '{VPeff,0,RPdrv};                        // drive output pins
assign N = '{VNeff,0,RNdrv};

endmodule

someone can help me to find the problem?

tanks