Post place-and-route SDF back-annotation fails when using Verilog multi-dimension array ports and internal nets

Dear all,

I'm working on a digital design with a top-level module that requires to declare some I/O ports with a combination of Verilog packed and unpacked array syntax in order to have a more compact and less error prone RTL code.

As an example, let suppose that my top-level module contains a port declaration and a sub-module instantiation such as

module MyModule(

   input  scalar_input,

   output scalar_output,

   output [9:0]  bus_output,

   output [9:0]  bundle_of_bus [31:0] ,

   other ports...  ) ;

   subModuleName   instanceName(

     .bus_output(bus_output), .bundle_of_bus(bundle_of_bus), other connections...) ;

  other stuffs here ...

endmodule

RTL simulations, synthesis and place-and-route flows work fine up to the final netlist and SDF export.

Unfortunately, when after place-and-route I try to perform gate-level simulations including SDF information the delay back-annotation fails. In fact all ports in the SDF file generated by EDI are exploded and escaped in form of

bundle_of_bus\[31\][0]

bundle_of_bus\[31\][1]  etc.

The gate-level Verilog netlist generated by EDI explodes instead the top-level module port declaration with the syntax

[9:0] \bundle_of_bus [0]

[9:0] \bundle_of_bus [1] etc.

whereas automatically-generated internal connections between I/O ports and instantiated cells use a condensed port-mapping like

instanceName( .\bundle_of_bus[31] ( \bundle_of_bus[31] ) ,

                       .\bundle_of_bus[30] ( \bundle_of_bus[30] )  etc. )

As a result of such a mess the SDF annotation fails, because Incisive can't properly access delays for these signals.

So the questions are :

1. is SDF annotation definitely unsupported by the Incisive simulator with such Verilog port declarations/internal connections ?

2. is there a way to fix this already during synthesis or place and route without editing the original RTL ?

I can't believe that Cadence tools don't support this syntax with its native Verilog language! :-)

Thanks in advance

Luca