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Create System Verilog library

Hi everyone,

I finally finish the model of my circuit in System Verilog. There are digital parts and analog parts, it's composed by 15 .sv file and one testbench. Now I would know if is possible to create a library of my model with this files. That means create a unique file, easy to edit, with the possibility of edit the parameter. I don't care if isn't a unique file, the important thing is create the library

Thank you very much for the future answers...

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