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Influencing the mapping process

Implophant

Dear community,

I’m currently struggling with a problem regarding formal verification of netlists. More specifically I want to use academic formal verification tools that either work with AIGER or DIMACS format to prove properties on synthesized netlists.

I haven’t found any tools or Cadence toolchain functionality that does a mapping (or synthesis) from Verilog netlists to either format or any other more abstract format, so I think I will need to find a way around.

I know that you can output the elaborated netlist (before technology mapping) which is already quite helpful. However, I was wondering if it is possible to either output the logic equations directly or to influence the technology mapping in a way that only AND, XOR, inverters, flip-flops and MUXes are used.

Best regards,

Hannes

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