Simulator ignores attributes during elaboration

Hey everyone,

Does anyone have a good experience with the instantiation of different cells in the same verilogams file?

I'm building a testbench and want to instantiate two instances that have the same name but exist in different libraries, one is schematic and the other one is veriloga.

What I did is the following:
     cell1
     (*
     integer library_binding = "Lib1"; 
     integer view_binding = "veriloga"; 
     *) dutvams (
           .x(dutvams_x), 
           .y(dutvams_y), 
           .z(dutvams_z)
     );
     cell2
     (*
     integer library_binding = "Lib2"; 
     integer view_binding = "schematic"; 
     *) dutsch (
           .x(dutsch _x), 
           .y(dutsch _y), 
           .z(dutsch _z)
     );
I'm also including the path to the veriloga model at the beginning of the verilogams file.

What happens is that when it compiles, it ignores the attributes in between the asterisks completely no matter what I'm tossing in, would only generate syntax errors if it's wrong and generates two schematic instances for Lib2.

When I change the name of the veriloga cell to a different name than the one for the schematic, it works properly.

I'm using virtuoso IC6.1.6.500

I don't know what I'm missing here! Any help would be appreciated, thanks :)