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[AHB eVC]How to send transfers with no IDLE cycles

J1EM1N

Hi, 

I want to send multiple SINGLE bursts with no intervals in between. like 2-2-2-2-2-2-2-2...

However, when I use the following source code, I got a couple of IDLE cycles like 2-2-0-2-2-2-0-2-0-2..., and I don't understand why. Can anybody help me?

(I am using non_blocking_write api, so there will be no 1 cycle loss between bursts.)

struct ahb_trans{

trans_type : vr_ahb_burst_kind;
trans_dir : vr_ahb_direction;
trans_size : vr_ahb_transfer_size;
trans_addr : vr_ahb_address;
trans_data : vr_ahb_data;

};

extend vr_ahb_master_seq_kind : [ MY_SEQ ];

extend MY_SEQ vr_ahb_master_seq {

!ahb_trans;

for i from 0 to 10 {

gen ahb_trans;

non_blocking_write( ahb_trans.trans_addr,
                                     {ahb_trans.trans_data},
                                      ahb_trans.trans_type,
                                      ahb_trans.trans_size);

};

};

* MY_SEQ will be used in MAIN sequence.

Appreciate any help.

Parents
  • I found the problem by setting the log verbosity to full.
    For some reason, some locked bursts are sent among all the bursts and an IDLE cycle was forced after each locked burst.
    Although I still don't understand why these unexpected locked bursts are inserted, I solve the problem by explicitly specify the burst.lock == FALSE;
    Hope this can help someone who encountered the same problem.
Reply
  • I found the problem by setting the log verbosity to full.
    For some reason, some locked bursts are sent among all the bursts and an IDLE cycle was forced after each locked burst.
    Although I still don't understand why these unexpected locked bursts are inserted, I solve the problem by explicitly specify the burst.lock == FALSE;
    Hope this can help someone who encountered the same problem.
Children
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