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  3. BlackBox RTL/GateLevel

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BlackBox RTL/GateLevel

jesolano
jesolano over 8 years ago

Hello!

I would like to create two black boxes one in RTL and another in GATE LEVEL, it can also be one like black box and the other not, however
the two DUTs have the same instance inside the module which accuses the following error:
ncelab: *E,MUNIT: More than one unit matches 'ABC'
attached is an example

//

//---FILE RTL.sv

module ABC;
initial begin

$display ("RTL FILE");

end
 
endmodule


//---FILE GATE_LEVEL.v


module ABC;
initial begin

$display ("GATE_LEVEL FILE");

end
 
endmodule


//--- FILE 3 TB.sv

module tb;

  ABC DUT_1();

  ABC DUT_2();

endmodule


//**** OBS:

///***********
//************ I want to create two black boxes one in RTL and another in GATE LEVEL,
//************ it can be one like black box and the other not, however
//************ the two DUTs have the same instance inside the module which accuses the following error:
                                                            
//************  ncelab: *E,MUNIT: More than one unit matches 'ABC':
//************    module designlib.ABC:rtl  (VST)
//************    module designlib.ABC:gate (VST).

//

Best regards!

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  • tpylant
    tpylant over 8 years ago

    Could you use the -bbcell/-bblist commands instead?

    -bbcell cell_name

    Ignore the specified cell when elaborating the design.

    For some simulations, you may want to ignore some parts of the design hierarchy and treat these parts of the hierarchy as black boxes to increase the performance of the simulator. One way to do this is to replace actual models in the design with empty (black box) modules. You can create empty modules for the actual modules you want to replace, compile these units into a library, and then write a configuration to specify the source description to be used to represent each instance in the design.

    The -bbcell option lets you blackbox all instances of a particular cell from the command line without changing the HDL or writing a configuration. The argument to this option is the Lib.Cell specification of the cell you want to ignore. All instances of the specified cell will be treated as a black box. 

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  • jesolano
    jesolano over 8 years ago
    Hello



    About error

    Elaborating the design hierarchy (incremental partition):
    ncelab: *E,MUNIT: More than one unit matches 'ABC':
    module worklib_gate.ABC:gate (VST)
    module worklib_rtl.ABC:rtl (VST)


    the command -bbcell can not solve the problem!



    #DUT_1 (RTL files)
    irun -mkprimsnap package1.sv dut.sv -bbox_create ./box1/ -name prim1 -nclibdirname INCA_PRIM1 -work worklib_rtl

    #DUT_2 (GATE LEVEL files)
    irun -mkprimsnap dut_2.v -bbox_create ./box2/ -name prim2 -nclibdirname INCA_PRIM2 -work worklib_gate

    #TB
    irun -access rwc -nclibdirname INCA_INCR -work worklib_both tb.sv -primbind -bbox_link ./box1 -bbox_link ./box2 -libmap lib.map -bbcell worklib_gate.ABC -top cfg -messages -gui


    When I use two DUTs with RTL files the bbox the work the same for two DUTs GATE LEVEL, but when I use onde DUT with RTL and another with GATE LEVEL does not work.


    Best Regards
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