• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. VPI: vpi_iterate does not access internal nets in SV code...

Stats

  • Locked Locked
  • Replies 3
  • Subscribers 66
  • Views 15610
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

VPI: vpi_iterate does not access internal nets in SV code despite vpiNet

Sporadic Crash
Sporadic Crash over 8 years ago

my vpi_iterate cannot access internal signals but the ports. Please help. Cadence Incisive version is 15.20.017.

I have following module (in SystemVerilog):

module my_block (
input logic a,
input logic b,
input logic c,
output logic z
);

logic intermediate_signal;

assign intermediate_signal = a & b;
assign z = intermediate_signal & c;

endmodule

I have written a VPI routine to grab all the signals in the block above:

#include <sv_vpi_user.h>
#define NULL 0

int dut_dump (char *str) {

vpiHandle handle_scope_iterator;
vpiHandle handle_scope_object;
s_vpi_value object_value;

vpi_printf ("Scope: %s\n", str);

object_value.format = vpiBinStrVal;

handle_scope_iterator = vpi_iterate(vpiNet, vpi_handle_by_name(str, NULL));

while (handle_scope_object = vpi_scan (handle_scope_iterator)) {
 vpi_get_value (handle_scope_object, &object_value);
 vpi_printf ("net: %s, value %s\n", vpi_get_str(vpiName, handle_scope_object), object_value.value.str);
}

 return (0);
}

When I instantiate the block my_block in a testbench and call the dut_dump in the testbench,

module tb ();
...
my_block dut (...);
...
initial begin
....
dut_dump("tb.dut");
...
end

endmodule

Simulation gives following:

ncsim> run

Scope: tb.dut
net: a, value 1
net: b, value 1
net: c, value 1
Memory Usage - 29.3M program + 25.1M data = 54.4M total

It does not iterate the internal signal intermediate_signal.

  • Where is my mistake?
  • Is VPI implementation for SystemVerilog in Incisive extended?
  • Do I use the correct header name?
  • Do I need a special switch to compile/elab/sim at Incisive?

  • Cancel
  • Tudor Timi
    Tudor Timi over 8 years ago

    You're not seeing 'intermediate_signal' because it isn't a net, but a variable. Simplistically put, nets are wires that connect variables. I'm not sure what the implicit rules are for describing whether a signal is a net or a variable, but I would assume that 'input logic a' is equivalent to 'input logic wire a', whereas inside the module body 'logic intermediate signal' is equivalent to 'logic var intermediate signal'.

    You can find more info about nets and variables in section '6.5 Nets and variables' of the 2012 LRM.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Sporadic Crash
    Sporadic Crash over 8 years ago
    I have found the reason by adding further debug which prints vpiTypes.
    For SystemVerilog the implementation of the version of the Cadence Incisive simulator I have used is that:-
    - the object types of logic for internal nets and output ports are of vpiType "vpiReg" (logic is a "reg" here, backward compatibility to Verilog-2001 etc)
    - the object types of logic for input ports are of vpiType "vpiNet" (logic is a "wire" here, backward compatibility to Verilog-2001 etc)

    That's why I could also not see the output port (because internally it was a "reg" even though decl was "logic"and driven by an "assign".

    The LRM 1800-2009 page 919 has more information about this (Part Three, "APIs", "37.17 Variables")
    Another simulator could return other types.

    So iterate for each of vpiType. Now I can see any object I am looking for.

    Thanks for your explanation though!
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Tudor Timi
    Tudor Timi over 8 years ago
    I would assume that the rules as to whether a simple 'logic' is treated as a 'reg' (i.e. variable) or 'wire' (i.e. net) are unambiguously described in the LRM and that a different simulator would return the same thing.
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information