Say now we have a covergroup which is intended to cover the 32-bit range of 'h0 ~ 'hFFFFFFFF.

```
logic [31:0] test_data;
covergroup test_cg @clk
option.per_instance = 1;
v: coverpoint test_data
iff(reset_n){
bins v_val_0 ={0};
bins v_val_n [5] = {[1:'hfffffffe]};
bins v_val_f = {'hffffffff};
illegal_bins v_illegal = default;
```

}
endgroup
test_cg t_cg = new();
always @(posedge clk)
begin
test_data = test_data + 'h400000;
t_cg.sample();
end
initial begin
test_data = 0;
end

The test_data is increased by 'h400000 at every posedge clk. So the covergroup above is supposed to reach 100% (except v_val_f ) very soon. However, the report give a big surprise as below, i.e. v_val_n[2] and v_val_n[4] are covered while v_val_n[3] is not covered at all. Anyone can help on this issue?

BTW, I'm working on IES-15.22 s024.

Thanks.

```
test_cg 71.43%, 71.43% (5/7) 269 covergroup test_cg (clk);
|--v 71.43% (5/7) 271 v: coverpoint test_data
| |--v_val_0 100.00% (19/1) 273 bins v_val_0 = {0};
| |--v_val_n[0] 100.00% (4284/1) 274 bins v_val_n[5] = {[1: 'hfffffffe]};
| |--v_val_n[1] l00.00% (4305/1) 274 bins v_val_n[5] = {[1: 'hfffffffe]};
| |--v_val_n[2] 100.00% (2163/1) 274 bins v_val_n[5] = {[1: 'hfffffffe]};
| |--v_val_n[3] 0.00% (0/1) 274 bins v_val_n[5] = {[1: 'hfffffffe]};
| |--v_val_n[4] 10O.00% (9598/1) 274 bins v_val_n[5] = {[1: 'hfffffffe]};
| |--v_val_f 0.00% (0/1) 275 bins v_val_f = {'hffffffff};
```